A low power dynamic pseudo random bit generator for test pattern generation - Details

Author：

Hou, Li-Gang (Hou, Li-Gang.) | Peng, Xiao-Hong (Peng, Xiao-Hong.) | Wu, Wu-Chen (Wu, Wu-Chen.) (Scholars：吴武臣)

Indexed by：

EI Scopus

Abstract：

Pseudo　random　bit　generator　is　widely　used　in　BIST　for　test　pattern　generation.　Typical　pseudo　random　bit　generator　adopts　linear　feedback　shift　register　(LFSR)　as　its　basic　circuit.　Dynamic　LFSR　(DLFSR[1])　which　has　better　cryptographic　properties　with　respect　to　typical　LFSR　consumes　more　power.　This　paper　forwards　a　low　power　DLFSR　(LDLFSR)　circuit　which　achieves　comparable　performance　with　less　power　consumption.　Typical　LFSR,　a　DFLSR　[1],　a　LDLFSR　are　compared　on　randomness　property　and　inviolability　property.　Multi-layer　perceptron　neural　networks　are　used　to　test　these　LFSRs＇　inviolability　property.　Result　shows　that　LDLFSR　keeps　comparable　performance　with　a　7%　power　reduction　and　a　5.6%　area　reduction.　©　2008　IEEE.

Keyword：

Shift registers Integrated circuits Low power electronics Multilayer neural networks Number theory Network layers

Author Community：

[ 1 ] [Hou, Li-Gang]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China
[ 2 ] [Peng, Xiao-Hong]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China
[ 3 ] [Wu, Wu-Chen]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China