Low power and high performance zipper domino circuits with charge recycle path - Details

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EI Scopus

Abstract：

A　charge　recycle　technique　is　proposed　in　this　paper　to　lower　the　dynamic　power　and　to　improve　the　performance　of　the　zipper　domino　circuits.　Zipper　domino　circuits　of　different　structures　are　designed　utilizing　this　technique　and　simulated　based　on　65nm,　45nm　and　32nm　BSIM4　SPICE　models.　The　simulation　results　show　that　the　power-delay　product　(PDP)　is　reduced　by　up　to　42.37%　as　compared　to　standard　domino　circuits.　What＇s　more,　a　power　distribution　method　is　introduced　in　Zipper　CMOS　full-adder　design.　Through　this　method,　the　charge　recycle　path　is　optimized　to　minimize　the　power.　©　2008　IEEE.

Keyword：

SPICE Low power electronics Timing circuits Recycling Delay circuits Fasteners

Author Community：

[ 1 ] [Wang, Jinhui]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China
[ 2 ] [Gong, Na]College of Electronic and Informational Engineering, Hebei University, Baoding 071002, China
[ 3 ] [Geng, Shuqin]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China
[ 4 ] [Hou, Ligang]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China
[ 5 ] [Wu, Chen]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China
[ 6 ] [Dong, Limin]VLSI and System Lab., Beijing University of Technology, Beijing 100022, China