Through　Silicon　Via　(TSV)　is　a　key　technique　in　wafer　manufacturing　and　3D　integration　for　wafer　level　package.　However,　due　to　the　large　mismatch　in　thermal　expansion　coefficient　under　thermal　loading,　stress　induced　by　TSV-Cu　may　drive　deformation　and　cracks　of　the　back-end-of-line　(BEOL)　layers.　Because　of　the　significant　difference　of　length　dimension　for　TSV　devices,　submodel　technique　is　used　to　investigate　the　reliability　issues　of　metal　interconnection　layers.　However,　the　validation　of　submodel　technique　for　complicated　TSV　structure　is　still　unknown.　The　aim　of　this　paper　is　to　validate　the　submodel　technique　in　TSV　structure.　In　this　study,　a　two　dimensional　finite　element　model　of　TSV　wafer　is　adopted　to　perform　the　numerical　analysis　with　finite　element　code　ABAQUS.　An　＂L＂　shaped　crack　is　pre-placed　in　the　edge　of　metal　interconnection　layers,　where　the　location　is　most　probableto　fail.　Two　typical　submodel　techniques　are　performed.　One　is　that　the　crack　is　embedded　in　the　global　model　called　submodel　technique　1,　and　another　one　is　that　the　crack　is　pre-made　in　local　model　called　submodel　technique　2.　J-integralis　computed　to　compare　the　differences　between　the　two　submodel　techniques.　The　effects　of　different　submodel　boundaries　on　J-integral　and　computation　efficiency　are　investigated.　It　is　found　that　J-integral　of　two　crack　tips　can　be　influenced　by　the　selection　of　the　suitable　boundary　for　both　submodel　techniques.　Less　time　consumption　is　needed　for　submodel　technique　1　compared　with　that　of　submodel　technique　2　in　linearly　elastic　model.