Through　silicon　via　(TSV)　is　a　crucial　interconnection　structure　in　3-D　integrated　circuits.　However,　protrusion　and　intrusion　of　TSV-Cu　caused　by　annealing　could　lead　to　cracking　and　failure　of　back-end-of-line　(BEOL)　layers　and　TSV　interconnects　due　to　mismatch　of　coefficient　of　thermal　expansion.　In　this　paper,　optimizations　of　TSV　interconnects　and　BEOL　layers　under　annealing　process　are　investigated　based　on　fracture　evaluation.　Influences　of　geometrical　factors　including　the　TSV　geometry　dimension,　the　distance　between　TSV　and　BEOL　layers,　and　pitch　size　of　Cu　via　on　energy　release　rate　and　J-integral　are　studied　for　TSV　interconnects　and　BEOL　layers　with　cracks.　Effect　of　material　properties　for　low　k　dielectrics　on　interfacial　fracture　of　BEOL　layers　and　TSV　interconnects　is　also　given.　Optimized　geometrical　factors　and　optimized　material　properties　of　low　k　dielectrics　are　presented　in　this　paper.　Fracture-based　method　sheds　a　light　on　emerging　electronic　packaging　optimization.