This　paper　presents　an　integrated　circuit　design　for　neural　recording　chip　with　integrated　CMOS　electrode　array.　The　implementation　of　on-chip　electrode　array　can　greatly　improve　the　implantability　of　neural　recording　systems.　The　chip　is　mainly　composed　of　a　neural　recording　analog　front　end　and　an　8x8　microelectrode　array　designed　in　CMOS　process　technology.　The　analog　front　end　of　the　neural　recording　circuit　adopts　chopper　technique,　which　effectively　reduces　the　lowfrequency　noise.　The　whole　circuit　has　been　designed　in　Cadence　using　the　SMIC　180-nm　CMOS　process.　The　simulation　results　show　that　the　signal　with　a　frequency　ranging　from　0-2kHz　and　the　amplitude　ranging　from　0-500　mu　V　can　be　independently　recorded　through　the　electrodes　with　a　control　terminal.　The　electrode　array　and　the　recording　analog　front　end　IC　are　partly　overlapped　using　different　metal　layers,　saving　the　chip　area.　The　chip　area　of　the　final　circuit　with　64　electrodes　is　only　1400　mu　m　x　760　mu　m.