Clock gating -A power optimization technique for smart card - Details

Author：

Zhou, Yongwang (Zhou, Yongwang.) | Peng, Xiaohong (Peng, Xiaohong.) | Hou, Ligang (Hou, Ligang.) | Wan, Peiyuan (Wan, Peiyuan.) | Lin, Pingfen (Lin, Pingfen.)

Indexed by：

EI Scopus

Abstract：

Power　consumption　is　a　key　issue　of　smart　card　whose　power　is　supplied　by　induced　currents.　This　paper　has　described　the　principle　of　the　clock　gating　technology　which　is　used　to　optimize　power　consumption　of　the　smart　card　in　RTL　level.　It　turns　out　that　the　total　power　consumption　has　been　reduced　by　40%　using　the　proposed　method,　without　obvious　increase　in　area.　The　smart　card　using　the　clock　gating　technology　is　verified　and　tested　in　180nm　process.　©　2014　IEEE.

Keyword：

Electric power utilization Clocks Smart cards

Author Community：

[ 1 ] [Zhou, Yongwang]Beijing Embedded System Key Lab, Beijing University of Technology, Beijing; 100124, China
[ 2 ] [Peng, Xiaohong]VLSI and System Lab, Beijing University of Technology, Beijing, China
[ 3 ] [Hou, Ligang]VLSI and System Lab, Beijing University of Technology, Beijing, China
[ 4 ] [Wan, Peiyuan]Beijing Embedded System Key Lab, Beijing University of Technology, Beijing; 100124, China
[ 5 ] [Lin, Pingfen]Beijing Embedded System Key Lab, Beijing University of Technology, Beijing; 100124, China

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Source ：

Year： 2014

Language： English

Cited Count：

WoS CC Cited Count： 0

SCOPUS Cited Count： 3

ESI Highly Cited Papers on the List： 0 Unfold All

WanFang Cited Count：

Chinese Cited Count：

30 Days PV： 9

Affiliated Colleges：

信息科学技术学院本学院/部未明确归属的数据

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