Analysis and design of double nesting gain boosted amplifier in 14 bits 50 MS/S pipeline ADC - Details

Author：

Wu, Yanwei (Wu, Yanwei.) | Peng, Xiaohong (Peng, Xiaohong.) | Dong, Yang (Dong, Yang.) | Liu, Miao (Liu, Miao.)

Indexed by：

EI Scopus

Abstract：

Because　of　high　sampling　rate　and　high　resolution,　pipeline　ADC　is　widely　used　in　system　on　chip　(SOC).　As　sampling　rate　and　resolution　increasing,　design　difficulty　is　increasing.　This　paper　analyzes　restricts　from　amplifier　in　Pipeline　ADC.　By　contrast　with　different　amplifiers,　this　paper　analyzes　and　designs　a　double　nesting　gain　boosted　amplifier　in　14　bits　50　MS/s　pipeline　ADC.　Under　1.2　V　power　supply,　this　amplifier　achieves　103　dB　DC　gain,　1.34　GHz　unity　gain　bandwidth,　88°　phase　margin.　Transient　simulation　result　shows　a　45μV　settling　time　error　in　10　ns.　The　total　consumption　is　24　mW.　©　2014　IEEE.

Keyword：

Programmable logic controllers System-on-chip Integrated circuit design Pipelines

Author Community：

[ 1 ] [Wu, Yanwei]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
[ 2 ] [Peng, Xiaohong]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
[ 3 ] [Dong, Yang]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China
[ 4 ] [Liu, Miao]VLSI and System Lab, Beijing University of Technology, Beijing; 100124, China