In　this　article,　the　degradation　mechanisms　of　radiation-hardened　vertical　double-diffused　MOSFETs　(VD-MOSFET)　experiencing　gamma　ray　irradiation　and　annealing　sequentially　experiment　device　and　simultane-ously　experiment　device　(Si-ED)　are　studied　and　compared.　Experiments　demonstrate　that　the　Si-ED　irradiated　with　gate　bias　(+12　V)　has　a　lower　oxide-trapped　charges　increment　(ANot)　and　higher　interface　states　increment　(ANit),　compared　to　those　of　sequential　experiment　device　(Se-ED).　However,　for　Si-ED　irradiated　with　drain　bias　(200　V),　it　shows　lower　ANot　and　ANit　than　those　of　Se-EDs,　which　is　similar　to　that　observed　in　the　case　of　devices　irradiated　with　three-terminal　bias　(200-V　drain　bias,　-10-V　gate　bias,　and　source　grounded).　In　addition,　for　all　cases,　it　is　seen　that　the　drain-biased　devices　own　a　larger　ANot　but　a　smaller　ANit,　compared　to　those　of　gate-biased　ones,　and　the　three-terminal-biased　devices　show　the　lowest,　especially　in　Si-ED.　As　a　result,　the　variations　of　ANot　and　ANit　could　cause　different　degradations　of　threshold　voltage,　breakdown　voltage,　leakage　current,　and　ON-state　resistance　of　devices,　which　would　inevitably　threaten　the　proper　functioning　of　electrical　systems.　Moreover,　in　this　article,　it　is　concluded　that　the　existing　standard,　i.e.,　accelerated　annealing　after　irradiation,　cannot　reflect　the　actual　radiation　reliability　of　devices.　Other　evaluation　methods　regarding　total　ionizing　dose　(TID)　need　to　be　further　explored　comprehensively.