Modern　processors　rely　on　advanced　memory　management　techniques　such　as　predicting　and　prefetching　to　bridge　the　processor-memory　gap.　However,　current　mechanisms　are　primarily　designed　for　a　specific　memory　hierarchy　level　or　access　pattern,　resulting　in　inefficiencies　for　diverse　workloads　with　mixed　memory　access　patterns.　To　address　this　challenge,　this　paper　proposes　DHCM,　a　Dynamic　Hierarchy　Coordination　Mechanism　that　intelligently　schedules　prediction　hierarchies　and　dynamically　optimizes　memory　access　processes　to　enhance　system　performance.　DHCM　integrates　a　hierarchy　coordination　mechanism　driven　by　a　State　Trigger.　This　mechanism　dynamically　leverages　system　feedback　to　prioritize　and　coordinate　memory　operations,　enabling　the　simultaneous　management　of　both　off-chip　load　requests　and　on-chip　cache　accesses.　Through　extensive　evaluations　on　the　ChampSim　simulator,　DHCM　demonstrates　its　adaptability　and　efficiency　with　an　average　IPC　improvement　of　34.08%　and　24.09%　on　single-core　and　multi-core　systems,　respectively.　Additionally,　DHCM　contributes　a　64.17%　miss　coverage　and　89.33%　DRAM-loads　reduction.