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Author:

Gong, Na (Gong, Na.) | Wang, Jinhui (Wang, Jinhui.) | Sridhar, Ramalingam (Sridhar, Ramalingam.)

Indexed by:

EI Scopus

Abstract:

In this paper, we propose an application-driven ALU design methodology to achieve high level of power efficiency for modern microprocessors. We introduce a PN selection algorithm (PNSA) which enables designers to select power efficient dynamic modules for different applications, based on the detailed analysis of dynamic circuits. Experimental results on ISCAS85 and 74X-Series benchmark circuits show that the power consumption of 8-bit ALU based on this approach can be reduced by 54%-60% for different frequency levels as compared to the conventional dynamic ALU design, demonstrating the effectiveness of the proposed method on application-driven custom ALU design. © 2013 IEEE.

Keyword:

Delay circuits Logic circuits Benchmarking Integrated circuit design

Author Community:

  • [ 1 ] [Gong, Na]University at Buffalo, State University of New York, Buffalo, NY, United States
  • [ 2 ] [Wang, Jinhui]VLSI and System Lab, Beijing University of Technology, Beijing, China
  • [ 3 ] [Sridhar, Ramalingam]University at Buffalo, State University of New York, Buffalo, NY, United States

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Source :

ISSN: 1948-3287

Year: 2013

Page: 185-188

Language: English

Cited Count:

WoS CC Cited Count:

SCOPUS Cited Count: 5

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 0

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