Due　to　high　density　requirement　in　electronics　packaging,　heterogeneous　integration　technology　is　used　widely.　Heterogeneous　integration　is　always　based　on　through　silicon　via　(TSV)　interposer　integrating.　Silicon　interposer　is　currently　the　mainstream　and　most　mature　interposer　technology,　which　has　been　studied　widely　and　presents　extensive　applications.　In　this　paper,　the　structure　and　process　of　wafer-level　TSV　interposer　is　proposed.　This　article　presents　an　equivalent　method　to　predict　the　warpage　of　wafer-level　silicon　interposer.　A　process-dependent　simulation　methodology　is　performed,　which　integrates　element　birth　and　death　technique　as　well　as　restart　technique.　The　validation　of　actual　model　and　warpage　of　wafer　during　fabrication　process　are　investigated　finally.　©　2021　IEEE.