Design of Verification Platform for CAN-FD IP Customized SRAM Controller Based on UVM - Details

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Abstract：

This　article　focuses　on　the　design　of　a　system-level　verification　platform　for　a　static　random-access　memory　(SRAM)　module.　The　SRAM　module　is　in　a　CAN-FD　SOC　chip.　The　SRAM　memory　controller　verified　by　the　verification　platform　in　this　paper　is　an　important　module　integrated　on　the　APB　SOC　chip　bus　for　basic　communication　with　CAN-FD　IP.　By　adopting　UVM　universal　verification　methodology,　a　complete　verification　platform　and　verification　environment　suitable　for　the　module　are　designed　and　built;　by　generating　constrained　random　test　excitation　signals,　the　function　of　the　controller　is　fully　verified,　and　the　results　can　be　automatically　compared　with　the　data.　The　results　show　that　the　verification　platform　can　greatly　reduce　the　development　time　of　verification　incentives,　simplify　the　verification　process,　shorten　the　verification　cycle　and　have　good　reusability.　©　2020　IEEE.

Keyword：

Controllers Programmable logic controllers System-on-chip Finite difference method Static random access storage Reusability Integrated circuit design

Author Community：

[ 1 ] [Yan, Shuaiqi]Vlsi and System Lab, Beijing University of Technology, Beijing, China
[ 2 ] [Geng, Shuqin]Vlsi and System Lab, Beijing University of Technology, Beijing, China
[ 3 ] [Peng, Xiaohong]Vlsi and System Lab, Beijing University of Technology, Beijing, China
[ 4 ] [Tang, Haonan]Vlsi and System Lab, Beijing University of Technology, Beijing, China
[ 5 ] [Zhang, Yan]Vlsi and System Lab, Beijing University of Technology, Beijing, China
[ 6 ] [Wang, Zifeng]Vlsi and System Lab, Beijing University of Technology, Beijing, China

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Year： 2020

Page： 218-222

Language： English

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ESI Highly Cited Papers on the List： 0 Unfold All

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30 Days PV： 4

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