Through　silicon　vias　(TSV)　has　been　given　an　extensive　attention　because　it　is　a　key　enabling　technology　for　three　dimensional　(3D)　IC.　In　this　paper,　the　thermal　stresses　of　the　fully　copper-filled　and　partially　copper-filled　vias　subjected　to　temperature　excursion　were　investigated,　and　the　analytical　solutions　of　stresses　in　the　copper　and　the　silicon　were　proposed.　The　solutions　have　been　used　to　investigate　the　effect　of　the　ratio　of　via　pitch　to　via　diameter　and　the　radial　thickness　of　copper.　A　two　dimension　finite　element　model　was　established　and　used　to　validate　the　analytical　solution.　The　results　suggest　that　the　analytical　solution　can　give　a　good　estimation　of　thermal　stress　in　the　copper　and　silicon;　the　stress　in　the　silicon　can　be　reduced　by　decreasing　the　radial　thickness　of　the　electroplated　copper;　the　stresses　change　linearly　with　the　temperature　excursion.